Japanese Patent Laid-open No. 2011-129816 (Patent Literature 1) discloses a conventional memory cell including a memory gate structure between two select gate structures (refer to FIG. 15 in Patent Literature 1). The memory cell includes a drain region connected with a bit line, and a source region connected with a source line, and also includes a first select gate structure, a memory gate structure, and a second select gate structure sequentially disposed on a semiconductor substrate between the drain and source regions. In the memory cell having such a configuration, the memory gate structure includes a charge storage layer surrounded by an insulative material. Data is programmed by injecting charge into the charge storage layer, and is erased by removing the charge from the charge storage layer.
To inject charge into the charge storage layer of such a memory cell, low bit voltage is applied from the bit line to a channel layer below the memory gate structure through the first select gate structure while voltage is blocked by the second select gate structure connected with the source line. Simultaneously, high memory gate voltage is applied to a memory gate electrode of the memory gate structure so that charge is injected into the charge storage layer due to a quantum tunneling effect caused by a large voltage difference between the bit voltage and the memory gate voltage.
In a nonvolatile semiconductor storage device including a plurality of memory cells arranged in a matrix of rows and columns and each having the above-described configuration, a memory gate line for applying voltage to each memory gate electrode is shared by a plurality of memory cells. With the configuration, when high charge storage gate voltage is applied to the memory gate line to inject charge into the charge storage layer of a particular memory cell, the high charge storage gate voltage is also applied to the memory gate electrode of any other memory cell sharing the memory gate line.
For this reason, in a memory cell into the charge storage layer of which charge is not to be injected, for example, high bit voltage is applied to the channel layer below the memory gate structure to reduce a voltage difference between the memory gate electrode and the channel layer, thereby preventing charge injection into the charge storage layer when high charge storage gate voltage is applied to the memory gate line.